Selector transistor promises broad impact across memory types

Selector transistor promises broad impact across memory types
Technology News |
Magnetic memory developer Spin Memory Inc. (Fremont, Calif.) has developed a type of selector transistor that it claims will be highly beneficial to DRAM, ReRAM and PCM memories as well as to MRAM.
By Peter Clarke

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The technology could have a major impact across a range of semiconductor ICs with annual sales of $100 billion, the company said.

Spin Memory states that its ‘universal selector’ is applicable across many established and emerging memory types and also curtails the so-called “row-hammer” problem in DRAMs while simultaneously reducing soft error rates (SER) and leakage.

Spin Memory is currently working with NASA on the applicability of this technology to develop low SER and row hammer-immune DRAM solutions and its technology has been presented to a JEDEC task force on the row-hammer problem.

As the cost of semiconductor scaling and innovation continues to rise, the industry has struggled to continue 2D memory scaling and performance — which limits advancements in areas such as AI and IoT. This limitation has given rise to 3D memory configurations or the layering up of multiple 2D memory planes. However, there remain vulnerabilities to soft-errors and deliberate hacking exploits.

Spin Memory’s selector is vertically-oriented epitaxial cell transistor that operates in full depletion. This allows the channel of the transistor to be electrically isolated from the silicon substrate and prevents trapped or migrating electrons from causing row hammer.

Row hammer is a hacking technique based on address selection in DRAMs and related to the sneak-path problem in memory arrays.

The “sneak-path” is well-known for memory arrays where lines and columns are simply selected. If unaddressed the sneak-path can lead to mis-reads of selected memory cells and cross-talk between adjacent memory cells. The solution has been to place a select device – typically a transistor or diode – at each memory node although this can create additional power consumption and increase die area. The row hammer attack is a DRAM hacking exploit which uses repeated use of particular memory access patterns to change the content of memory cells not originally addressed.

Next: memory leaking


Leakage current is inherent in DRAM and conventionally addressed by refresh but additional leakage occurs during a row-hammer attack which causes cells to leak enough charge to change its content within a refresh interval. The row hammer effect has been used to change bit values and thereby to achieve privilege escalation and launch network attacks.

Spin Memory claims the universal selector does more than just address row hammer disturb. It allows different configurations of memory circuits and improvements in area density. It can improve DRAM array density by 20 to 35 percent by allowing a 4F2 bitcell configuration. For MRAM, ReRAM and phase-change RAM the selector allows 1T1R memory cells with between 6F2 and 10F2 area, or up to 5x increased area density with minimal additional wafer processing costs.

In turn the improved memory density will enhance  such applications as artificial intelligence, virtual reality and edge computing, Spin Memory said.

“Row hammer is one of the leading issues in DRAM reliability and security, and has long been a frustrating plague on the memory industry. As DRAM’s longstanding major disturb problem, row hammering is only becoming more of a problem as cells shrink,” said Charlie Slayman, IRPS 2020 technical program chair, in a statement issued by Spin Memory. “Spin Memory’s Universal Selector offers a novel way to design vertical cell transistors and has been presented to the JEDEC task group evaluating solutions to the row hammering problem.”

Next: Presentation


Spin Memory claims that beyond the density improvements for DRAM and emerging memory types the vertical selector will bring MRAM up to SRAM-like performance while retaining the added benefit of being non-volatile. High performance MRAM that is denser than SRAM and non-volatile will offer a memory option that could allow major changes in logic architecture (see ARM, Applied, seek to replace SRAM with MRAM).

Spin Memory will share additional technical details its universal selector at the virtual 31st Magnetic Recording Conference on Thursday, August 20 at 10:40 a.m. PDT. Kadriye Deniz Bozdag, Spin Memory’s manager of MRAM testing, will give an online presentation. Anyone interested in signing up for the event and watching the presentation online can register here.

Related links and articles:

www.spinmemory.com

News articles:

ARM, Applied, seek to replace SRAM with MRAM

MRAM revolution could trigger new ARM architecture

ARM, Applied send more money to Spin Memory

Weebit Nano seeks ‘selector’ for discrete memory market entry

Will Sony launch cross-point nonvolatile memory?

China’s XTX adopts Weebit’s ReRAM

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