TSMC completes Japan chiplet research cleanroom

Technology News |
By Peter Clarke

Leading foundry TSMC has completed construction of the cleanroom at its 3DIC R&D centre in Ibaraki prefecture northeast of Tokyo, Japan.

The clean room is in the Tsukuba Center of the National Institute of Advanced Industrial Science and Technology (AIST).

It was reported that TSMC planned to invest about $190 million in a 3DIC R&D facility in February 2021 (see Report: TSMC plans Japan R&D center ahead of packaging facility). The facility could come ahead of a larger chiplet assembly facility in Japan, which could help with Japan’s goal of increased domestic manufacturing of chip components.

The TSMC Japan 3DIC R&D Center is being set up to research three-dimensional silicon stacking and advanced packaging technologies in materials science. These technologies will enable system-level innovations to increase computing performance and integrate more functionality, opening a new path for driving semiconductor technology forward in addition to the industry’s conventional path of shrinking transistor size.

The TSMC Japan 3DIC R&D Center will work in collaboration with Japanese partners, domestic research institutes and universities possessing strengths in semiconductor materials and equipment.

“The Japan 3DIC R&D Center is a perfect example of this collaboration in action. By bringing TSMC together with Japan’s talent, we will empower each other to make breakthroughs together,” said C.C. Wei, CEO of TSMC, in a statement.

Related links and articles:

News articles:

Report: TSMC plans Japan R&D center ahead of packaging facility

Report: TSMC, Japan to share cost of Tokyo chip facility

Chiplet-savvy TSMC to build $10 billion assembly and test plant

Huawei proposes vertical transistor for 3D-DRAM


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