Moortec: Embedded PVT monitoring from 40nm to 7nm

By Moortec
Download White Paper
Share:

This white paper discusses challenges of design at 16nm and below including maufacturing variability, high current density, self-heating and excessive guard-banding. Also temperature inversion of performance below 40nm node. The use of performance, voltage and temperature (PVT) monitoring helps cope with complexity and the paper discusses multiple ways it can be employed. Read More



Disclaimer: by clicking on this button, you accept that your data might be communicated to this company. If you do not want us to communicate your data, please update your details on your profile

Download White Paper
White Papers
10s