5nm tape outs to come 1H19, says TSMC

January 24, 2019 //By Peter Clarke
5nm tape outs to come 1H19, says TSMC
Despite an oversupply of 7nm process production capacity foundry giant TSMC is pressing on with the introduction of 5nm-node production, which will make use of extreme ultraviolet (EUV) lithograpy.

TSMC CEO CC Wei told analysts on a conference call to discuss fourth quarter financial results that N5 customer tape-outs are on schedule for the 1H19 with volume ramp of production in the 1H20.

Throughout the conference call its was said that while the 5nm ramp might not be as steep as previously expected most of the customers working with TSMCat 7nm are also discussing 5nm designs. Wei added that at 5nm the market is expanding. "We expect more applications in HPC to adopt N5. Thus, we are confident that N5 will also be a large and long-lasting node for TSMC," said Wei.

Wei also noted that TSMC's 7nm chip client portfolio broadening. Originally focused on smartphone applications the 7nm node is now being targeted for chip designs for applications such as HPC and automotive. "Customer tape-outs activities at N7 continue to be strong despite the cautious macro outlook," Wei said.

At the same time TSMC executives discussed the introduction of N7+, a second generation of the 7nm production process that makes use of EUV lithography. "Our N7+ yield rate is progressing well and comparable to N7. N7+ volume production is scheduled to begin in second quarter this year. As I have stated before, we are working with several customers on N7+ to support their second and third wave product designs.

Related links and articles:

www.tsmc.com

News articles:

Report: Order downturn to leave TSMC with spare 7nm capacity

Cadence gets EDA certification for TSMC's 5nm and 7nm+ FinFET processes

Update: IMEC, Cadence tape out first 5nm test chip


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.