Speedcore is a flexible FPGA architecture that can be built with densities ranging from less than 10,000 look-up tables (LUTs) to up to two million LUTs plus large amounts of embedded memory and DSP blocks and designed specifically to be embedded
in SoCs and ASICs. When compared to standalone FPGAs, Speedcore eFPGAs deliver considerably smaller die area, the potential for higher bandwidth as well as higher performance, lower power and lower overall system costs.
The test chip included 40,000 LUTs, 1Mbit of RAM and 72 DSP64 blocks and ran at 500MHz clock frequency across all operating conditions. It was verified using the Speeedcore16t
Validation board, a platform available to potential customers to fully evaluate Speedcore eFPGA capabilities.
Some customers already have Speedcore IP and initial licensing fees of Speedcore on 16nm contributed to Achronix' sales in 2017, according to Steve Mensor, vice president of marketing at Achronix. Speedcore IP deliveries occurred as early as 2016 and tape-outs were expected by about mid-2017 (see Achronix branches out into FPGA IP with TSMC ).
"Yes, the tape-outs did happen although they pushed out into the second-half of 2017. And we've had the test chip for a while," Mensor said that 2018 would see royalties flow from Speedcore.
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