Achronix, Facebook, NXP working hard for a chiplet future
The OCP has claimed it is making progress in the development of a path to chiplet-based electronics assembly from both the technical and business points of view.
Chiplet’s are a design style where multiple die are included in a single package, often on a silicon interposer. This leverages 2.5D and 3D assembly and packaging techniques being introduced by foundries and test and assembly houses. The method allows multiple smaller chips to be designed in their own optimal process and brought together but economies of scale are expected to be realised if physical, electrical and data interfaces can be agreed across industry sectors.
The use of smaller die has benefits for yield.
Back in March 2019, an OCP subproject known as Open Domain-Specific Architecture (ODSA) was chartered with the development of a chiplet-based architecture for manufacturing electronics.
The OCP held a meeting in Amsterdam, The Netherlands, in September 2019 where a number of steps in defining that chiplet-based architecture were presented and discussed. These included the specification of interfaces, link layers and descriptions of a marketplace and exchange for IP and chiplet entities.
The ODSA subproject’s mission is to define an open interface and architecture that enables the mixing and matching of silicon chiplets from different vendors via an open marketplace onto a single SoC.
To that end ODSA has multiple working groups.
Aquantia, Avera Semi, Netronome and zGlue are working in the ODSA PHY interface group which has analysed multiple candidate inter-chiplet interfaces and defined its own “bunch-of-wires” (BoW) interface version 0.7.
The ODSA Proof of concept (PoC) group is planning to deliver a prototype by the end of the year made multiple interoperable, interchangeable boards that would represent chiplets to test progress in interfaces. Group members include participants from Achronix, Cisco, Facebook, Netronome, NXP Semiconductors and zGlue.
Next: Don’t forget business
Finally the business working group, which looks at business and licensing issues, has released version 0.9 of the specification for a chiplet design exchange (CDX). The CDX is an extension of the zGlue Exchange Format (ZEF), which defines how to describe chiplets and data sharing. Participants in this group include zGlue, Ayar Labs, Microsoft Azure, and Netronome.
The CDX provides echoes of the Virtual Component Exchange (VCX) formed by the Scotland’s national economic development agency, Scottish Enterprise, in 1998 with a view to promoting chip design in Scotland around IP cores. Initially VCX had a prestigious list of corporate backers including ARM, Cadence, Mentor, Siemens, Toshiba and TSMC. However, the idea failed to gain much traction in an industry sector that was already trading IP cores via direct two-party contracts and which nearly always accompanied by a degree of engineering customization.
Aaron Sullivan, director of hardware engineering at Facebook, said: “We are observing new architectures emerging that solve for rapidly changing workloads currently not well-fit for a traditional large-scale integration approach to design. These new architectures provide improved approaches to rapidly and cost-effectively develop workload-specific products. We believe an open chiplet-based architecture being developed within the ODSA community provides a pathway towards achieving these goals, while enabling continued performance gains.”
OCP has hosted three previous workshops for the ODSA subproject in conjunction with Samsung, Intel and IBM.
“Creating new open standards for chiplet-based architecture and interoperability is an important step forward to enabling emerging applications, like machine learning, that require compute resources at unprecedented scale,” said Kushagra Vaid, a senior engineer who works on hardware infrastructure to support Microsoft’s Azure cloud computing service.
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