The OCP has claimed it is making progress in the development of a path to chiplet-based electronics assembly from both the technical and business points of view.
Chiplet's are a design style where multiple die are included in a single package, often on a silicon interposer. This leverages 2.5D and 3D assembly and packaging techniques being introduced by foundries and test and assembly houses. The method allows multiple smaller chips to be designed in their own optimal process and brought together but economies of scale are expected to be realised if physical, electrical and data interfaces can be agreed across industry sectors.
The use of smaller die has benefits for yield.
Back in March 2019, an OCP subproject known as Open Domain-Specific Architecture (ODSA) was chartered with the development of a chiplet-based architecture for manufacturing electronics.
The OCP held a meeting in Amsterdam, The Netherlands, in September 2019 where a number of steps in defining that chiplet-based architecture were presented and discussed. These included the specification of interfaces, link layers and descriptions of a marketplace and exchange for IP and chiplet entities.
The ODSA subproject’s mission is to define an open interface and architecture that enables the mixing and matching of silicon chiplets from different vendors via an open marketplace onto a single SoC.
To that end ODSA has multiple working groups.
Aquantia, Avera Semi, Netronome and zGlue are working in the ODSA PHY interface group which has analysed multiple candidate inter-chiplet interfaces and defined its own "bunch-of-wires" (BoW) interface version 0.7.
The ODSA Proof of concept (PoC) group is planning to deliver a prototype by the end of the year made multiple interoperable, interchangeable boards that would represent chiplets to test progress in interfaces. Group members include participants from Achronix, Cisco, Facebook, Netronome, NXP Semiconductors and zGlue.
Finally the business working group, which looks at business and licensing issues, has released version 0.9 of the specification for a chiplet