The neural network IP is optimized for 'camera-first' autonomous driving applications AImotive said. The Apache5 SoC is being developed for automotive OEMs and their tier one suppliers.
The aiWare NN is architected to scale to more than 100TOPS and to be highly autonomous thereby requiring less host CPU and shared memory resources. AImotive claims the architecture can achieves up to 95 percent sustained efficiency for complex NNs applied to large data inputs such as high definition cameras.
Supporting Khronos’ NNEF as well as open standard ONNX inputs, the comprehensive aiWare SDK compiles binaries with no need for low level programming of DSPs or MCUs. It includes automated floating point FP32 to integer INT8 conversion, alongside a portfolio of DNN analysis tools.
The Apache5 comprises four Cortex-A53 cores and imaging signal processor capable of supporting image sensors up to 5Mpixel resolution. In-built features including noise correction, high dynamic range, LED flicker mitigation, defogging, format conversion, dead pixel correction, lens distortion correction, and parking guidance.
The Apache5 IEP will be supplied to AEC-Q100 Class 2, and be certification-ready for ISO26262.
AImotive said it will work with NextChip to achieve certifiable level 2 to level 4 computer vision to L4 solutions using the Apache5 IEP, leveraging AImotive’s extensive experience and in-house knowledge of designing advanced AI solutions and complex DNNs for safety-critical automotive applications.
"Nextchip has spent more than 20 years designing advanced image processor chips and related technologies for a wide range of vision systems, including supplying several leading automotive customers," said YoungJun Yoo, CMO of Nextchip.
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