Cadence gets EDA certification for TSMC's 5nm and 7nm+ FinFET processes

October 02, 2018 // By Julien Happich
Cadence Design Systems announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs.

As part of the collaboration, the Cadence digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC 5nm and 7nm+ processes, and the corresponding process design kits (PDKs) are now available for download. Customers using Cadence’s implementation, signoff and custom/analog tools are already in production with 7nm+ projects, and there are multiple design projects underway with early 5nm customers.

For the 7nm+ process, the Cadence full-flow includes the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution and Physical Verification System (PVS). For the 5nm process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution.

The digital and signoff tools provide EUV support at key layers and associated design rules that enable customers to achieve power, performance and area (PPA) savings at these advanced nodes. Some of the newest enhancements for the 5nm and 7nm+ process include via pillar-aware synthesis and feed forward guidance with the Genus Synthesis Solution as well as a pin-access control routing method for cell electromigration (EM) handling and statistical EM budgeting support.

The Cadence-certified custom/analog tools for the latest versions of the TSMC 5nm and 7nm+ process technologies include the Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option and Spectre Circuit Simulator, as well as the Virtuoso custom IC design platform, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso ADE Product Suite and Virtuoso Integrated Physical Verification System. The Layout-Dependent Effect (LDE) Electrical Analyzer is also certified for 7nm+, and the collaboration on 5nm is ongoing.

The Virtuoso Advanced Node Platform methodology consists of features and functionality required for creating 5nm and 7nm+ designs including mixed-signal functional verification, reliability analysis and an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet power, multi-patterning, density and EM requirements. Cadence also introduced new features including end-to-end constraint support, dummy insertion and advanced MIMCAP support specifically for the 5nm process.

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