SkyWater Technology Foundry Inc. (Bloomington, Minnesota) has produced a physical design kit for a carbon-nanotube based three-dimensional chip design platform from DARPA. The PDK is the results of a project with DARPA and Massachusetts Institute of Technology (MIT) that has now entered its second phase. The 3DSoC program is expected to accelerate AI and advanced computing across use cases in autonomous vehicles, medical/healthcare diagnostics, edge computing, wearables, and IoT applications.
The first phase focused on transferring the Carbon Nanotube Field Effect Transistor (CNFET)-based 3DSoC technology into SkyWater’s 200mm production facility (see SkyWater partners for carbon nanotube design service). Phase two will focus on refining manufacturing quality, yield, performance, and density.
The DARPA 3DSoC program, which began in 2018, has realized several technical achievements after running a wide variety of test chips to improve CNT manufacturability and reliability.
Work from the 3DSoC program – the BEOL integration of CNFETs + RRAM and SRAM + RISC-V compute core were discussed at the virtual 2020 Symposia on VLSI Technology and Circuits in June 2020.
Notably, the technology enables the monolithic integration of stackable tiers of CNT-based logic and RRAM to realize a high-density, high-bandwidth SoC architecture, all with low temperature fabrication techniques. While this is anticipated to accelerate AI and advanced computing, it also opens new dimensions of innovation and potentially enables backend logic integration with non-silicon substrates. This development could open up the possibility of monolithic heterogeneous integration with on-chip logic for imaging, smart sensors, power management, and many other undiscovered applications.
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