Does the protracted time to market create a risk that a product, such as an NRAM with a DDR4 interface, could have missed its market opportunity by the time it comes out?
"No, for a couple of reasons," said Schmergel. One is that DDR5 is only at version 0.3; the final version is not yet decided. Secondly it would be relatively simple amendment to the design to swap out a DDR4 interface for a DDR5 interface once the details are agreed. Thirdly, Schmergel asserted, there will be a long tail for DDR4 applications.
But what about taking NRAM on beyond 28nm CMOS? Is Nantero engaged with FinFET or FDSOI semiconductor manufacturing proponents, or both? "We have done a lot of work studying the scalability of our memory. In our labs we have demonstrated bit cells at 15nm by 15nm and a detailed model shows switching operation should go down beyond 5nm."
As NRAM only requires a single mask to define where the CNT layer goes and a small number of process steps it can be fabricated at low cost and is compatible with both 3D multilayer architectures and multi-level cell operation. "One of the great things about NRAM is that it is largely process independent. We're not affiliated with either camp – FinFET or FDSOI – but equally applicable," said Schmergel.
Because each CNT memory bit contains 100s or 1000s of CNTs it is possible to make multi-level cells. "We have made progress with multiple bits per cell but it does end up being a lower speed memory. Still faster than flash but below DRAM, so these things are a trade-off," Schmergel said.
Schmergel is hopeful that further licensee disclosures can be made in 2018. The company's website states that two infrastructure systems companies, six additional semiconductor licensees and multiple leading foundries will be announced "soon." But until those companies start selling chips there is little incentive for them to go public on their involvement with Nantero, Schmergel said.
Next: Lining up applications