It requires a different way of thinking about chips, both in terms of their role within systems and their life cycle, and it shows how rapidly on-chip monitoring IP is changing from what was only recently a simple, binary protection mechanism.
Moortec is a licensor of embedded intellectual property (IP) for process, voltage and temperature (PVT) monitoring, targeting planar and FinFET CMOS processes on 40nm, 28nm, 16nm, 12nm and 7nm.
The company was formed by Crosher and colleagues in 2005 with the aim to do something significant in semiconductors. They had previously been working for Zarlink Semiconductor, one of the manifestations of what had been GEC-Plessey Semiconductors. Some 15 years later Moortec is still relatively small but has roughly doubled in head-count over the last three years to reach 55 people.
But back in 2005, staffed with just a few analog circuit designers, the company decided to bide its time and start off by doing design services. This had the advantage of providing a revenue stream immediately, allowing the company to avoid debt or taking on equity funding. However, that startup phase ended up lasting five years.
"We've been profitable from day one and grew the company organically. We were developing our own design flows and processes and through that gained insight into the IP business," said Crosher. "And we realized that analog design was going to have an important role to play in advanced digital nodes."
In 2010, while still conducting analog and communications designs for clients, Moortec started developing reusable IP, Crosher said. "We'd noticed that up until that point, monitoring technology had tended to be developed in-house," said Crosher. This was an opportunity for Moortec to relieve clients of what was becoming non-differentiating activity and help them focus on the rest of the complexity of getting 65nm and 40nm chips designed.
Next: analog IP for digital engineers