CEO interview: Preparing for the on-chip feedback revolution: Page 2 of 5

June 22, 2020 //By Peter Clarke
CEO interview: Preparing for the on-chip feedback revolution
Stephen Crosher, co-founder and CEO, of Moortec Semiconductor Ltd. (Plymouth, England), is preparing his company to play its part in providing the essential feedback for dynamic modification of the behaviour of individually characterized chips.

Crosher added that up until that time most monitoring had been thermal, providing basic on-off protection, either of the system, or of the processor chip, or both. "But we also realised that monitoring for more advanced nodes could become more sophisticated and more specialized, giving us a market opportunity."

Crosher said other analog IP licensors were not competing in this area. They could be general IP or specialized IP but either way tended to be focus on what could be thought of as functional IP, such as phase locked loop (PLL), or serializer-deserializer (SERDES) blocks. "We were analog circuit designers selling to digital design teams. We packaged the IP to make it easier for them to integrate into the digital domain," explained Crosher.

As a result, Moortec found its niche and decided to focus on on-chip process, voltage and thermal monitoring. And Moore's Law and the increasing digital chip complexity has provided plenty of work for the company. "Over the subsequent ten years the requirement has evolved," said Crosher.

"To begin with it was a bit of a tick-box exercise for on/off or safe-mode operation. But it evolved to in-chip monitoring underpinning overall optimization schemes," said Crosher. Most notably this included the use of temperature and voltage monitoring for use in dynamic voltage and frequency scaling (DVFS) schemes.

A next step is multiple points of monitoring as an essential part of the functionality. "We are at 7nm and 5nm and heading down to 3nm and at this point I think of the chips as being like a Formula One car. Without sensors, a Formula one car would explode in short order."

Moortec recently announced its distributed sensor subsystem aimed at TSMC's 5nm  manufacturing process and that specifically supports this richer, fine-grained sensing (see Moortec recasts in-chip thermal sensor for TSMC N5 process).

Being able to monitor a chip and choke back performance brings other benefits, particularly for multiprocessor chips, Crosher added.

It allows wider process variability to be tolerated in manufacturing and therefore better yields and lower costs per chip. It can allow supply voltage reduction and improve tolerance to voltage spikes and IR-drops. Thermal monitoring allows greater gate densities than would otherwise be possible. By monitoring for hot spots and redirecting processing Moortec's IP can reduce thermal stress and risks of electromigration of metals and increase reliability. It can be used for wear-levelling across multicore processors.

Next: Beyond PVT


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