Cerfe Labs claims ferroelectric RAM, FET breakthrough

June 25, 2021 // By Peter Clarke
Cerfe Labs claims ferroelectric RAM, FET breakthrough
ARM spin-off Cerfe Labs Inc. (Austin, Texas) has produced an update on its progress with ferroelectric materials, hailing its work as a breakthrough that will allow ferroelectric non-volatile memory to scale to current CMOS process nodes.

Cerfe executives Lucian Shifren and Greg Yeric and Professor Carlos Paz de Araujo of partner company Symetrix Corp. (Colorado Springs, Colo.) claim to have identified a spontaneous ferroelectric material with a low enough anneal temperature to be suitable for use with FeFET and FeRAM devices manufactured using leading-edge CMOS process nodes. The authors go on to state the technology could be used for DRAM and 3D-NAND applications and even for non-volatile logic transistors, which could impact the design of highly energy efficient systems.

The update does not identify the material or materials but talks of "true," or spontaneous ferroelectric materials that provide low leakage, and low voltage ferroelectrics without strain.

Devices are made using a combination of engineered ferroelectric materials and device engineering, according to the update. The results presented have a highest anneal temperature of 400C that needs only be maintained for minutes rather than hours. Cerfe claims it has multiple "knobs" it can operate to tune the material – including anneal temperature, composition, sintering and doping – and that is making progress towards an anneal temperature of 350C.

"We call the result 'SNAP Ferro'. SNAP Ferro can be integrated between two electrodes for a standard FeRAM like device and is also compatible with all CMOS nodes with the addition of an industry-standard interfacial oxide," the authors state.

The results cover the hysteresis window adjustable between 0.2V and 8V, leakage current claimed to be at commercially viable levels and high-temperature operation.

The update does not provide details of minimum planar geometries used to define SNAP FeRAM and FeFET devices, but given that the work has been done in laboratory they are unlikely to be close to the leading-edge. The authors state the SNAP Ferro stack is 40 to 50nm thick but this is limited by the lab's spin-on process and can be made thinner.

Next: Cerfe's up

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