But whatever the background, ARM's loss is Cerfe Labs' gain and the technology under development is certainly intriguing.
It is a technology that I and one or two others have been keeping an eye on for the best part of a decade. It relies on the doping of a transition metal oxide that can be "born-on" as a metal but when hit with an applied voltage and critical current density switches to an insulating state. This so-called correlated electron or electron orbital Mott transition is reversible, inherently fast and takes place throughout the bulk of a material. It should also have a low current density during the setting process.
That in turn brings likely benefits over the myriad forms of ReRAM that are currently out in the wild and attracting investment. But research proofs grind exceedingly slowly and researchers have limited access to the tools needed to make critical dimensions in line with leading-edge manufacturing processes.
So far the research team has moved the original Symetrix Corp. (Colorado Springs. Colo) work at 5 microns diameter down to 47nm and have developed more than four transition metal oxide material systems. What Cerfe needs to do over the next couple of years is to prove these switches at 30nm, 20nm and 10nm. By then leading foundry TSMC is likely to be offering a nominal 3nm manufacturing process with a 10nm half-pitch.
Greg Yeric, CTO at Cerfe Labs, is bullish about the technology's ability to scale. He said: "Deep dimensional scaling coupled with multi-level cell capability and 3D crossbar stacking capability are combined, without trade-off, with fast and low power switching, and an unheard-of temperature window. All that comes in a one-film deposition that we have shown works in spin-on, PVD [plasma vapor deposition] or ALD [atomic layer deposition]. So a large swath of memory applications are on the table at this point, from edge AI to automotive to HPC [high-performance computing], and they can flexibly be addressed in manufacture from spin-on with possibly etch free process to high precision ALD."
Yeric offered that the team's nanometer-scale devices show a greater than 50x on/off ratio and are created in the low-resistance state with forming-free operation. His assessment is that the indicators are that the 2nm CMOS compatible bit cell with a select transistor is possible, with multi-level cell operation as a bonus.
Next: Stacking up