Chip design at 5nm is one third more costly than at 7nm

June 04, 2020 //By Peter Clarke
Chip design at 5nm is one third more costly than at 7nm
The cost of designing complex SoCs is increasing by 30 to 50 percent per node, according to Semico Research, Artificial intelligence in EDA could help the analysis company asserts.

The complexity is such that less design teams are getting designs right first time. In addition, designs are taking longer while the windows of opportunity in the market are shrinking.

Semico states that the average silicon design cost for SoCs across all geometries was $4.8 million in 2019. While this may seem a small amount it must be remember that much cost is in the mask sets that are used to produced these designs, particularly at the leading edge.

What is more stark is that silicon design costs for a first-time effort multicore SoC at the 5nm node are projected to be 31 percent higher than for a similar project at 7nm.

And software design costs for multicore SoCs through the 2nm process node are forecast to grow at a 51.1 percent compound annual growth rate. IP Integration costs are rising at a 56.8 percent CAGR through the 5nm node.

Semico concludes that EDA tools with artificial intelligence and machine learning could produce design cost savings of between 25 and 30 percent.

"The introduction of EDA tools that include some level of AI functionality aimed at making designers more efficient and productive in their design efforts is a promising trend. As we have seen with other types of design tools introduced to the market, once deployed there is a continual improvement in performance and functionality," says Rich Wawrzyniak, an analyst with Semico, in a statement. "It is reasonable to expect the same from the new AI-empowered EDA tools with continual improvements being offered to designers. We believe this will be especially notable in the areas of SPICE modeling, simulation, verification and architectural exploration."

Related links and articles:

www.semico.com

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