Chiplet manufacturing gains interface bus upgrade, PHY generator

July 20, 2020 //By Peter Clarke
Chiplet manufacturing gains interface bus upgrade, PHY generator
The CHIPS Alliance consortium has released the AIB version 2.0 draft specification and startup Blue Cheetah has released an AIB interface IP generator.

CHIPS Alliance, a consortium advancing common and open hardware for interfaces, processors and systems, has released the Advanced Interface Bus (AIB) version 2.0 draft specification on GiHub. A 2018 startup, Blue Cheetah Analog Design Inc. (San Francisco, Calif.), has developed a parameterizable physical interface generator for IP, which also addresses AIB.

AIB was donated to CHIPS Alliance by Intel to to encourage chiplet-style manufacturing across the semiconductor industry (see www.chipsalliance.org). As a result the AIB standard is an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package. AIB is suitable for designing SoCs, FPGAs, SerDes chiplets, high-performance ADC/DAC chiplets, optical networking chiplets and more.

Draft version 2.0 of AIB, just released, has six times the edge bandwidth density of AIB 1.0 through increases in the per-wire line rate and the number of I/Os per channel. Additionally, with smaller microbumps AIB 2.0 can use as little as half of the current microbump array area.

AIB can be a primary enabler of chiplet-style manufacturing, which in turn allows semiconductor developers to choose best-in-class manufacturing processes for different functions.

"As companies increasingly rely on chiplets to keep up with the latest computing requirements and workloads for different applications, AIB will make it easier to integrate silicon IP with other chiplets into a single device to deliver new levels of functionality and optimization," said Zvonimir Bandić, chairman of the CHIPS Alliance, in a statement.

The AIB specification has long been used by Intel for its own multi-die components and has been adopted by DARPA’s Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program.

Blue Cheetah’s AIB PHY generator for die-to-die connections generates netlist, GDS, LEF, LIB, and behavioral models across a multitude of process design kits (PDKs).

"Reducing barriers to entry in developing custom silicon will be critical for the growth, adoption, and success of the chiplet movement," said Krishna Settaluri, CEO, Blue Cheetah Analog Design, in a statement.


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