Chiplet-savvy TSMC to build $10 billion assembly and test plant

June 02, 2020 //By Peter Clarke
Chiplet-savvy TSMC to build $10 billion assembly and test plant
Chiplet-style manufacturing could be what lies behind a plan at leading foundry Taiwan Semiconductor Manufacturing Co. Ltd. to spend $10 billion on an IC assembly, packing and test facility in Miaoli, northern Taiwan.

According to a local report that references Miaoli county magistrate Hsu Yao-Chang's Facebook page, TSMC is planning to spend NT$300 billion (about $10 billion) to build the IC packaging and testing plant.

The general plan to build a plant at Miaoli has been on TSMC's roadmap since 2018 and in November 2019 the plan passed an environmental impact assessment, enabling the foundry to begin construction of the fab in 2020 as scheduled. The plant is scheduled to be completed in May 2021 with operations set to start in mid-2021, the reports state.

The sum of money, as yet unconfirmed by TSMC, is large for a packaging and test plant. It is likely that this represents a life-time spend for an advanced packaging technology facility. There is a reference to the development on a Miaoli County government page here.

"TSMC has not disclosed the investment amount and the schedule of the facility," a TSMC spokeperson told eeNews Europe in response to an emailed request for information. The spokesperson also said: "The plan was first announced sometime late 2018 and got environmental assessment approval in Nov. 2019. We expected to start the construction after we get the license in June. We have also disclosed that the project is expected to bring 2500 jobs."

Such a large outlay, it it comes to pass, would be consistent with the way in which the distinctions between "front-end" and "back-end" manufacturing are blurring at the leading-edge of digital IC manufacturing and with the use of chiplets. Chiplet-style manufacturing allows the most cost-effective manufacturing processes to be used for each circuit block and then assembles the 'chiplets' together, often on a passive or active silicon interposer, to create multi-die components.

TSMC already provides some IC packaging and testing services at plants in Taoyuan, Hsinchu, Taichung and Tainan. This is largely related to 3D packaging and multi-die component techniques such as CoWoS and InFO. For more conventional assembly and test TSMC's customers can use independent service providers such as ASE, Amkor, Nanium, SPIL and JCET Group (see ASE dominates top 25 ranking of chip packagers).

But with its experience in CoWoS and InFO TSMC is an enthusiastic proponent of chiplet manufacturing and it provides an opportunity for the company to keep more of the added value in house.

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