Ferroelectric memory startup aims at GloFo's 22FDX

October 26, 2016 //By Peter Clarke
Ferroelectric memory startup aims at GloFo's 22FDX
The Ferroelectric Memory Co. (Dresden, Germany) was at Semicon Europa in Grenoble, France, to show off its 64kbit non-volatile memory array manufactured in 28nm CMOS and threw its hat into the ring as a contender to provide the 22FDX process with an embedded memory option.

The company, a spin-off from the nano- and micro- laboratory (NaMLab) at the Technical University of Dresden, is making use of the recently discovered ferroelectric effect in silicon-doped hafnium dioxide. The company has made progress over the last year in terms of establishing hafnium ferroelectric memory as design choice for embedded nonvolatile memory in 28nm processes and below.

The 64kbit active array was developed with Globalfoundries Inc. and is the subject of a paper due to be presented at the upcoming International Electron Devices Meeting (IEDM) in San Francisco in December. Meanwhile FMC is seeking funds. Having received more than €4 million (about $4.4 million) in government grants the company says it is looking approximately €2 million more Series A funding round.

Because a thin film of hafnium oxide is used as the dielectric in advanced CMOS processes it means the technology has a much reduced premium in terms of mask and process steps compared with embedded flash and magnetic RAM. It is also space efficient compared with these alternatives and ferroelectric memory is field-driven rather than current driven making it highly energy efficient.

The research team from FMC and Globalfoundries are due to describe how ferroelectric FETs have been integrated with Globalfoundries’ commercially available low-power 28nm gate-first HKMG CMOS platform. The hafnium-based FeFET gate stack can be optimized independently from the 28nm technology and this allows mixed placement of CMOS and FeFET devices in the same circuit is possible. High-temperature data retention (≤250 degrees C) and endurance up to 10^5 cycles were demonstrated, according to a precis of the upcoming paper.

The read/write voltage scheme is currently in the region of 3 to 5V with 10nm hafnium dioxide films. These voltages will scale with thickness and will be reduced with further optimization and films down to 5nm thickness. "I/O voltage is something we can achieve," said CEO Stefan Mueller

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