Technical CAD simulations of a new forksheet device show 10 percent performance boost and 20 percent cell area reduction compared to gate-all-around nanosheet devices.
IMEC has been championing the forksheet transistor, along with the use of a buried power rail as a way to push semiconductor scaling to the 2nm manufacturing process node and the research firm is due to present at the 2019 IEEE International Electron Devices Meeting.
The forksheet device has recently been proposed by IMEC as an extension of vertically stacked lateral gate-all-around nanosheet devices (see Here comes the forksheet transistor, says IMEC ). A key part of the design is the introduction of a dielectric wall in between the P- and NMOS devices before gate patterning. This wall physically isolates the p-gate trench from the n-gate trench, allowing a much tighter n-to-p spacing.
The device structure being presented at IEDM targets a 2nm node with gate pitch of 42nm and a 5-track standard cell library with a metal pitch of 16nm. The proposed design includes scaling boosters such as buried power rails and wrap around contacts. Compared to a nanosheet device, a 10 percent speed gain (at constant power) and a 24 percent power reduction (at constant speed) is reported.
The performance boost can be partly explained by a reduced miller capacitance, resulting from a smaller gate-drain overlap. Finally, the n-to-p separation reduction can be used to reduce the track height from 5T to 4.3T. Further layout optimization exploiting the structure of the device enables more than 20 percent cell area reduction. When implemented in an SRAM design, the simulations reveal a combined cell area scaling and performance increase of 30 percent for 8nm p-n spacing.
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