Ansell said that right now the digital standard cells are available but that the project intends to add analog and RF circuits, and compilers for SRAM and flash memory. The second shuttle run will be early in 2021 and they should follow on a quarterly basis thereafter.
Those who are interested to submit their designs must send a Git respository URL containing their design to efabless.com. They will receive an email back if their design is accepted.
"An open, manufacturable PDK was the main blocker in a fully open flow between RTL and a physical chip, and we're extremely excited to see that blocker removed," said the FOSSi Foundation, in a statement.
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