The first SoIC chiplets are expected to enter mass production in 2022. Google's interest is in autonomous driver assistance systems (ADAS), according to a Nikkei report. AMD would create closely-coupled processor and memory systems to gain competitive advantage against Intel in the data center.
TSMC has introduced a service it calls 3DFabric that comprises a family of 3D silicon stacking and packaging technologies. It includes the established CoWoS and InFO packaging styles, which were used for die-to-die and die-to-interposer packaging. Xilinx was an early adopter of CoWoS. 3DFabric also adds a third tier that TSMC calls SoIC for System on Integrated Chips (SoIC).
SoIC broadens the ability to stack die-to-die with high-density vertical stacking and minimum resistance, inductance and capacitance in the interconnect. This translates into an ability to stack and link different types of known-good-die, such as processors, memory, sensors and passives into a single packaged component allows the use of multiple manufacturing processes that are best in class for a particular function and reduces interconnect and power consumption.
It has implications for electronic design automation (EDA) which becomes a 3D rather than a 2D task and for design partition. It also has implications for the semiconductor supply chain where foundries have previously focused on front-end processing and a set of back-end service providers performed assembly and test services. TSMC, already the world's largest foundry and most valuable chip company, will be taking on both roles for some customers who use its leading-edge processes.
Next: TSMC does the packaging