Julien Ryckaert, program director of 3D hybrid scaling, discussed the potential roadmap for transistor development down to 2nm and beyond at the IMEC Technology Forum. He suggested the forksheet could come into deployment at a nominal 2nm node. This would be ahead of the nanosheet-based and vertically staked complementary FET (CFET), another idea that has previously been touted by IMEC (see IMEC presents 'n-over-p' complementary FET proposal).
However, there remains uncertainty as to whether any or all of the three remaining leading-edge semiconductor companies will adopt which of these technically demanding and therefore expensive schemes to achieve higher performance-power-area (PPA) trade-offs.
The three companies that remain in the leading-edge logic game are Intel, Samsung and Taiwan Semiconductor Manufacturing Co. Ltd.
The questions over adoption are key because at 1nm IMEC is foreseeing a move to radically different device concepts and new functionalities to meet new applications. To make the adoption of a novel device structure worthwhile it really needs to be more long-lived than a single production node. So a move to the forksheet or the CFET for one generation of miniaturiation may not be economic or provide enough time for the supporting ecosystem to develop.
Natural evolution from fin to fork. Source: IMEC.
So, a company that sticks with incremental improvements on the FinFET could win out over the company that goes for the forksheet or the CFET. On such bets vast fortunes could be won or lost.
Next: Long-lived nodes