IEDM to discuss 2D materials, 3D architectures

October 15, 2021 // By Peter Clarke
IEDM to discuss 2D materials, 3D architectures
This year's International Electron Devices Meeting includes highlight papers from IBM and Samsung on 3D structures and Intel on embedded ferroelectric RAM, amongst many others.

The technical program for this year's IEDM has been posted with theme to reflect two industry trends: the use of so-called 2D materials – having thicknesses measured in atoms –  in order to further miniaturize transistors; and the use of a variety of 3D architectures to incorporate more features and performance from transistors and circuits.

After a virtual event in 2020 due to the Covid-19 pandemic the 67th IEDM returns to being an in-person event. It is due to be held December 11 to 15, 2021 at the Hilton San Francisco Union Square hotel.

A team from IBM and Samsung have built vertical CMOS devices using so-called vertical transport nanosheet field effect transistors (VTFETs) on bulk silicon. The vertical devices offer the opportunity for continued scaling beyond what is possible in horizontal transistor manufacturing. This is because the gate length and spacer size – two elements that determine gate pitch (the distance between transistors) – can be optimized in ways that aren’t possible horizontally.

The VTFETs also promise excellent voltage and drive current as a result of reduced parasitic losses compared with laterals designs.

The researchers made functional ring oscillators as test circuits, which showed about a 50 percent reduction in capacitance versus lateral design reference. (Paper #26.1, “Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices,” H. Jagannathan et al., IBM/Samsung).

Researchers from Belgian Research institute IMEC usually author many papers at IEDM and this year of particular note is a paper on a concept that has been in development at IMEC for several years – that of moving power rails to beneath the transistor plane

Separating power and logic interconnect should bring the benefit of reducing interconnect complexity and allowing smaller chip designs. The researchers drawn from IMEC and ASM International have experimented with different metals both for the buried power rail (BPR) and for low-resistence contacts needed between the BPR and the through-silicon-vias that take power out

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.