There are 21 papers that touch on ferroelectric materials and FeFET memory compared with 12 on MRAM and this is despite the success that MRAM has achieved as an embedded non-volatile memory option at leading foundries. Hafnium-oxide has the advantage that it is already in use in semiconductor manufacturing as an insulating dielectric. If comparable or superior performance to MRAM can be obtained and scalability demonstrated it could gain the advantage.
Here is a quick round up for the ferroelectric FET highlights from IEDM. There are that are two sessions – 4 and 18 – devoted to the topic and several other papers spread throughout the program.
Session 4 is on modelling and simulation of ferroelectric switching dynamics and device applications while Session 18 is on ferroelectric memory. The session kicks off with authors from the universities of Florida, Southern California and Boston presenting on a ferroelectric tunnel junction memory based on the interface between single atomic layer graphene and a 4nm-thick layer of the van der Waals material CuInP2S6 (CIPS). Such an FTJ is promising for both NVM applications and neuromorphic computing, the authors claim. By sandwiching the FTJ layer between electrodes it is possible to the modulate the barrier resistence.
At IEDM the authors are due to present simulations of these heterojunctions, verified by laboratory experiments that show a record-high tunneling electroresistance ratio of 6 x 10^7.
Session 18 kicks off with authors from Kioxia – formerly Toshiba Memory – describing a HfO2-based FeFET and ferroelectric tunnel junction and its suitability for reinforcement learning for an in-memory computing architecture.
The final paper (18.6) in the session comes from authors at Ferroelectric Memory GmbH, NamLab, Applied Materials and Globalfoundries Dresden. This looks at how programming can be used to achieve multi-level cells in FeFET memory. There is the additional claim that appropriately selected programming algorithms can improve the FeFET endurance performance and variability for small device geometries. The influence