IEDM MRAM round up

November 12, 2020 //By Peter Clarke
IEDM MRAM round up
With the support of multiple foundries magnetic RAM is establishing itself as a replacement for flash memory as an embedded non-volatile memory (NVM) for nodes at 28nm and below.

At this year's virtual International Electron Devices Meeting there are 12 papers in the technical program outlining the suitability of MRAM for on-chip memories in microcontrollers and microprocessors.

At the 28nm node authors from Samsung are due to describe the use of embedded MRAM as a frame buffer with a density of 0.08 square millimeters per Mbit. At that density it can provide a 47 percent area saving compared with SRAM (paper 11.2)

Globalfoundries and TSMC each describe their latest additions of MRAM non-volatile memory to manufacturing process technologies. Globalfoundries is set to report a 40Mbit embedded-MRAM for 22nm FDSOI process for low-power industrial-grade applications and the possibility of automotive applications with 20 year data retention and 1 million endurance cycling (paper 11.3). Globalfoundries began offering MRAM on 22FDX process in 2016 (see Globalfoundries offers embedded MRAM on 22nm FDSOI).

Meanwhile TSMC is ready to report an 8Mbit STT-MRAM macro in its 16nm FinFET manufacturing process that achieves a write access time of 9ns from -40C to 125C at Vdd of 0.8V (paper 11.4 and see TSMC offers 22nm RRAM, taking MRAM on to 16nm).

Globalfoundries authors also set to present papers on magnetic tunnel junction stack engineering for high-speed applications and on device technology co-optimization (DTCO) for manufacturability (papers 11.6 and 13.5).

A team from Georgia Institute of Technology aided by researchers from the universities of Stanford, Minnesota and Cornell report on an exploration of materials for spin-orbit torque MRAM, which represents a potential next-generation refinement of MRAM (paper 13.6).

A research team from European research institute IMEC will follow through on that possibility with the presentation of an SOT-MRAM technology for embedded NVM at the 5nm node. The paper (24.5) is set to explore different bit-cell architectures that can achieve close to SRAM performance with bit-cell area reductions of up to 40 percent.

The MRAM papers show some signs of progress but their smaller numbers compared with ferroelectric field effect transistor (FeFET) memories could be indicative of one or two things. It could show a reduced appetite to publish on MRAM by commercial entities because it is close to market or it could show that the additional masks and materials requirements are proving an inhibition that is not present with hafnum-oxide based FeFET.

Early registration ends on November 20. Up until then non-members of the IEEE can register for access to the event at a reduced rate of US$330 rising to US$380 thereafter.

Related links and articles:

www.ieee-iedm.org

News articles:

IMEC, ferroelectrics prominent in virtual IEDM program

Globalfoundries offers embedded MRAM on 22nm FDSOI

TSMC offers 22nm RRAM, taking MRAM on to 16nm

ARM forms spin-off to pursue CeRAM memory

MRAM startup Antaois raises $11 million


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