The research will focus on the assembly of smaller 'chiplets', the optimization of interconnect and on bonding and stacking technologies for 3D ICs, Leti said. The team work will particularly target high performance computing (HPC) applications.
The use of chiplet assembly and 3D packaging is thought to be one of the directions semiconductor design will take as the cost-efficiency of pursuing leading-edge miniaturization diminishes.
In 2019 Intel introduced its Foveros 3D-stacking technology which is being introduced in Intel Core processors. However, typically such 3D-stacking is either done die-to-die or using a passive silicon interposer, which can limit the number of chiplets that can be assembled.
Leti has developed an active silicon interposer substrate technology that allows chiplets to communicate with each other directly whatever their relative positions in the assembly.
Leti reported on its technology in February 2020 at the International Solid-State Circuits Conference. The paper discussed a component with 96 processor cores organized across six chiplets. The chiplets were attached to a 65nm active silicon interposer. At June 2020 IEEE Electronic Components and Technology Conference Leri received the best paper award for its work on active silicon interposer.
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