"RISC-V (pronounced five) was really the result of a summer academic program to create a processor that could be used to teach processor design in 2010," O'Connor explained. The obvious choices for teaching had been the x86 and ARM but their instruction sets had become complicated and there were IP and license issues so using them for teaching was not really possible. The the primary motivation was for something simple but that used the best ideas for academia. It took until 2013 to develop and May 2014 was when the specification was first frozen.
But the reason that RISC-V Foundation was formed to look after the ISA specification was because companies liked the open-ness and wanted to make use of the architecture in the commercial environment, O'Connor added. "There are now more than 100 organizations in the RISC-V Foundation. We call it an open instruction set architecture rather than open-source hardware. It's not the first. SPARC is open and there have been others."
And that is an important distinction because although ISA is open and use of it is royalty free there is a lot of work to be done creating an implementation of that ISA; in creating a full-blown CPU from an ISA. The companies that do that work – such as SiFive, Cortus, GreenWaves, Microsemi and others – will want paying for it just as you pay a microcontroller vendor whether it is based on ARM or another ISA.
So why would a user go for a RISC-V based chip rather than a more established architecture?
Next: Clean-slate architecture