Latchup in CMOS and its prevention

January 19, 2015 // By Keith Sabine
Latchup in CMOS and its prevention
Keith Sabine, product manager at EDA firm Pulsic, discusses circuit latchup and its prevention.

Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either inherent in the design or triggered by voltage spikes on IO pads that could forward bias PN junctions to which they were connected.

To understand why latchup can occur, consider the simple inverter in Figure 1.

Figure 1: A typical CMOS inverter cross section, showing parasitic devices.

The inverter consists of two MOS transistors. Also placed somewhere nearby (not necessarily between the devices as in the diagram) are well and substrate taps to bias the well to VDD and the substrate to VSS. There are also parasitic bipolars: a vertical PNP device formed by the P+/N well/P Substrate junctions, and a horizontal NPN device formed by the lateral N+ / P substrate / N well junctions.

A simplified schematic of the parasitic elements is shown in Figure 2. The shunting resistors Rwell and Rsub represent the effective resistance from the well tap to the PNP base and the substrate tap to the NPN base.

For the circuit to latch up, several conditions must be met1.

1  The transistor current gain product of Qn and Qp must be greater than 1 such that the structure will remain latched.

2  Both emitter-base junctions of Qn and Qp must be forward biased to initiate and sustain latchup.

Next: Simplified schematic.



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