Six FPGAs cover the range from 40,000 to more than a million LUT-4 equivalent cells. Prices start at $10 for the smallers CCGM1A1device in volume quantities. The low cost for these FPGAs also means that Cologne Chip is predicting these chips are well-suited to university projects; another aspect of the continental independence that they support.
The FPGA family uses a novel configurable logic unit known as the Cologne Programmable Element (CPE). Each CPE consists of a look-up-table (LUT) tree with 2 by 4-inputs. Each CPE configurable as 2-bit full-adder or 2x2 multiplier providing fine-grained support for reduced-resolution applications in such areas as artificial intelligence and machine learning. There is fast configuration from off-chip using a 4bit SPI interface operating at clock frequency of up to 100MHz.
The core logic can operate at 0.9, 1.0 V, 1.1 V depending on which of three modes the FPGA is set to – low power, economy or speed. Multiple clocking schemes are supported. The FPGAs support arbitrary sized multipliers and memory-aware applications can use block RAMs with bit widths of 1 to 80 bits. General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5V GPIOs can be configured as single-ended or LVDS differential and a 2.5Gbit/s SERDES interface is available.
GateMate FPGAs are supported by EasyConvert software that enables the transfer of existing FPGA designs without re-synthesis. Place and route software maps ports the design into GateMate FPGA and a static timing analyser provides critical-path information. The design can be simulated using Verilog netlist and SDF timing extraction.
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