Also on the manufacturing front, Maxim told its investors it will utilize a 90nm CMOS geometry for its preferred platform. Its denser logic would support new-generation PMICs. The proprietary process—developed in conjunction with an unnamed foundry partner—takes advantage of many years of “deep submicron R&D,” says Doluca. This would be something of a first, since—unlike digital CMOS, whose performance increases with shrinking geometries—analog does not scale. Consequently, custom PMIC makers continue their work in 0.18- and 0.13-micron CMOS. The 90nm process would more appropriately be considered a 2017 platform, Maxim acknowledged, as a very small proportion of the company’s production use the process now.
Stephan Ohr is a former director for Semiconductor Research at Gartner, where he tracked analog and power management ICs with forecasts, market share analyses, and client advisories. Prior to his 10 years at Gartner, Ohr was founding editor-in-chief of Planet Analog and an editor on EE Times.
This article originally appeared on EE Times
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