MIT researchers have presented a chip designed specifically to implement neural networks at the International Solid State Circuits Conference in San Francisco.
"Deep learning is useful for many applications, such as object recognition, speech, face detection,” said Vivienne Sze, a professor in MIT's Department of Electrical Engineering and Computer Science whose group developed the chip.
The chip is called Eyeriss and the idea is that training up for the network for specific functions could be done "in the cloud" and then the training configuration – the weighting of each node in the network could be exported to the mobile device.
The chip has 168 cores each with its own memory with idea that by minimizing the frequency with which cores need to exchange data with distant memory banks. When such exchanges are off-chip in particular it consumes much time and energy.
The chip has a circuit that compresses data before sending it to individual cores and each core is also able to communicate directly with its immediate neighbors, so that if they need to share data, they don’t have to route it through main memory.
The final key to the chip’s efficiency is a circuit that allocates tasks across cores. In its local memory, a core needs to store not only the data manipulated by the nodes it’s simulating but also data describing the nodes themselves. The allocation circuit can be reconfigured for different types of networks and applied across the network at the start of running the application.
As part of the ISSCC presentation the MIT researchers used Eyeriss to implement a neural network that performs image-recognition.
"In addition to hardware considerations, the MIT paper also carefully considers how to make the embedded core useful to application developers by supporting industry-standard [network architectures] AlexNet and Caffe," said Mike Polley, a senior vice president at Samsung’s Mobile Processor Innovations Lab.
The MIT researchers' work was funded in part by