In an interview on the side lines of the ARM Research Summit held in Cambridge this week, he said that if MRAM could achieve a sufficient speed-up to rival SRAM it would be a game-changer for logic design.
Yeric told eeNews Europe that spin-orbit torque MRAM (SOT-MRAM) technology, currently in R&D around the world, might get up to the appropriate speed-endurance trade-offs to allow its introduction into core logic. If it does, it will provide not only the chance to retrofit established ARM architectures with dense non-volatile memories but also to rethink how to design processor cores from the system-level down.
The current generation of MRAM, spin transfer torque MRAM or STT-MRAM, is not really able to do that, although it is starting to be considered as a cache memory option on microcontrollers (see Startup tapes out MRAM-based MCU ). But research institute IMEC has manufactured the follow-on MRAM technology, spin-orbit torque MRAM, on 300mm-diameter wafers. IMEC reported that while STT-MRAM switching speed is limited to 5ns, the SOT-MRAM demonstrated reliable switching down to 210ps (see IMEC makes spin-orbit torque MRAM on 300mm silicon ).
The ability to freeze computing processes on-chip, retain state while drawing no power and then resume, would have considerable consequences, Yeric said. "It would require a new processor architecture. I think we would be adding a new processor line; something that could address a different power envelope in the IoT space; working without batteries by using harvested energy," Yeric told eeNews Europe .
The full interview is available here (see ARM's Greg Yeric on memory, logic and making it ).
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