The N1 SDP supports designs for ARM's Neoverse series of processors. Neoverse is ARM's attempt to demonstrate that it can offer processor cores that are purpose designed for networking infrastructure applications. ARM is scheduled to launch 'Ares' on 7nm in 2019, 'Zeus' on 7nm in 2020 and 'Poseiden' on 5nm in 2021. With each introduction, the performance is expected to increase by 30 percent (see Reports: ARM discloses roadmap performance in Taiwan ).
The Neoverse N1 SDP is a7nm infrastructure-specific system development platform, enabling asymmetrical compute acceleration through the CCIX interconnect architecture.
Moortec's sensors support design for increased reliability and enhanced performance optimization by enabling schemes such as DVFS, AVS and power management control systems. Moortec's analog and mixed-signal IP designs are delivered to ASIC and System on Chip (SoC) technologies within the automotive, AI, IoT, datacenter, digital television, high-performance computing and networking sectors.
The increase in gate density, which equates to an increase in power density, is a major contributor to the heating of semiconductor devices manufactured on advanced node CMOS technologies
"Through our collaboration, we are helping to enhance performance and efficiency of ARM's next-generation compute technology on 7nm. By contributing our high accuracy embedded sensing fabric to the development of the Neoverse N1 SDP, we’re enabling customers to benefit from higher performance and reliability within machine learning, artificial intelligence and data analytics applications," said Moortec CEO, Stephen Crosher.
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