RTL Architect cuts design time, scales, improves results, says Synopsys

March 16, 2020 //By Peter Clarke
RTL Architect cuts design time, scales, improves results, says Synopsys
Synopsys has announced an EDA software product for design analysis, optimization and sign-off, called RTL Architect that it describes as being "physically aware."

It operates at the register transfer level (RTL) and uses a beefed-up data model and prediction engine to allow better results to be delivered in half the time of previous sign-off tools, the company said. Synopsys and ARM are collaborating on RTL Architect to accelerate the development of next-generation cores.

The unified data model delivers higher capacity and scalability allowing the tool to be applied to full-chip hierarchical RTL design flows on contemporary multibillion transistor designs.

In current design practice RTL can be a poor indicator of downstream power-performance-area and this can cause developers to have to go back and rewrite the design to meet the goals of various vertical markets such as artificial intelligence and automotive.

RTL Architect has a prediction engine built-in and enables RTL designers to pinpoint bottlenecks in their source code to improve RTL quality. For existing users of Synopsys PrimePower at the gate-level, PrimePower RTL power estimation is also available, enabling a consistent RTL to signoff power analysis flow.

"Synopsys' RTL Architect will enable us to quickly explore and validate various architectures at the RTL stage and identify the best one without having to worry about late-stage surprises," said Hideyuki Okabe director of digital design technology at Renesas Electronics Corp., in a statement issued by Synopsys.

Related links and articles:

www.synopsys.com

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