The roadmap was rolled out at a one-day annual Samsung Foundry Forum event held in Santa Clara, California, May 24.
The processes include an 18nm FDSOI process node and manufacturing processes at 8, 7, 6, 5 and 4nm. At 4nm Samsung plans to introduce a post-FinFET process that it calls MBCFET for multi-bridge channel FET.
Samsung described the MBCFET as a gate-all-around FET (GAAFET) that uses a "nanosheet" to overcome physical scaling and performance limitations of the FinFET architecture. The description is also reminiscent of multiple nanowire-within-fin designs that have been shown by research groups such as IMEC.
Samsung is expected to start so-called "risk production" of MBCFETs in 2020 in the 4nm low-power plus (LPP) process. It remains unclear as to what sort of materials Samsung intends to use in the channel. Germanium doping or in higher quantities as a strain agent is one possibility that is already mainstream in FinFET processes but research has also considered the inclusion of III-V materials or carbon as means of improving transistor action at these tiny geometries.
"To successfully compete in today’s fast-paced business environment, our customers need a foundry partner with a comprehensive roadmap at the advanced process nodes to achieve their business goals and objectives," said Jong Shik Yoon, executive vice president of foundry business at Samsung Electronics, in a statement.
Next: Between now and 2020