Samsung to introduce nanosheet transistors in 3nm node

May 28, 2018 //By Peter Clarke
Samsung to introduce nanosheet transistors in 3nm node
Samsung Electronics has announced an update to its process node per year roadmap with the introduction of a 3nm gate-all-around (GAA) that will reportedly arrive some time in or after 2022. Above are 5nm nanosheet transistors reported by IBM at VLSI Technology Symposium in 2017.

The 3nm process comes in two variants – 3GAAE and 3GAAP – standing for early and plus and will be based on the nanosheet construction with multiple lateral ribbon-shaped wires in a fin. This nanosheet design has been much discussed by research institute IMEC as a follow-on to the FinFET and was researched by IBM in collaboration with Samsung and Globalfoundries.

"Applying GAA structure to our next generation process node will enable us to take the lead in opening a new smart, connected world, while also to reinforcing our technology leadership," said Charlie Bae, executive vice president and head of foundry sales and marketing at Samsung Electronics.

In addition, Samsung said its 7nm 7LPP process is on target to be ready for production in the second half of 2018. Key circuit IP cores are under development, aiming to be completed by the first half of 2019.  One implication of this admission could be that Samsung will begun production of its own Exynos processors for smartphones in 2018 but that availability to fabless chip companies through Samsung foundry may have to wait until 2019. It may also be that Samsung will introduce the process in 2018 without using extreme ultraviolet lithography (EUVL) and insert EUVL in 2019

However, the 6nm process tipped at the equivalent event in 2017 has disappeared from the roadmap (see Samsung adds 4nm and FDSOI processes to roadmap).

Samsung announced:

7LPP (7nm Low Power Plus): 7LPP, the first semiconductor process technology to use an EUV lithography solution, is on track for first production in 2018.

5LPE (5nm Low Power Early): Through further innovation from the 7LPP process, 5LPE will allow greater area scaling and ultra-low power benefits. It is a deviation from the 5LPP scheduled last year but should enter risk production in 2019.

4LPE/LPP (4nm Low Power Early/Plus: FinFET technology will be extended to the 4nm process and arrive in 2020 and 2021.

Next: And on to 3nm

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.