The technology could have a major impact across a range of semiconductor ICs with annual sales of $100 billion, the company said.
Spin Memory states that its 'universal selector' is applicable across many established and emerging memory types and also curtails the so-called "row-hammer" problem in DRAMs while simultaneously reducing soft error rates (SER) and leakage.
Spin Memory is currently working with NASA on the applicability of this technology to develop low SER and row hammer-immune DRAM solutions and its technology has been presented to a JEDEC task force on the row-hammer problem.
As the cost of semiconductor scaling and innovation continues to rise, the industry has struggled to continue 2D memory scaling and performance — which limits advancements in areas such as AI and IoT. This limitation has given rise to 3D memory configurations or the layering up of multiple 2D memory planes. However, there remain vulnerabilities to soft-errors and deliberate hacking exploits.
Spin Memory's selector is vertically-oriented epitaxial cell transistor that operates in full depletion. This allows the channel of the transistor to be electrically isolated from the silicon substrate and prevents trapped or migrating electrons from causing row hammer.
Row hammer is a hacking technique based on address selection in DRAMs and related to the sneak-path problem in memory arrays.
The "sneak-path" is well-known for memory arrays where lines and columns are simply selected. If unaddressed the sneak-path can lead to mis-reads of selected memory cells and cross-talk between adjacent memory cells. The solution has been to place a select device – typically a transistor or diode – at each memory node although this can create additional power consumption and increase die area. The row hammer attack is a DRAM hacking exploit which uses repeated use of particular memory access patterns to change the content of memory cells not originally addressed.
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