IMEC is presenting its use in multiple papers at this week's 2019 SPIE Advanced Lithography Conference.
SIS is an existing technique, used in directed self-assembly (DSA) in which the photoresist is infiltrated with an inorganic element to make it harder and more robust, thereby enhancing the patterning performance in a variety of ways.
It comes at the cost of an additional step but during a full pattern transfer in a TiN layer, imec observed a improvement of 60 percent for intrafield local critical dimension uniformity (LCDU) and 10 percent for line edge roughness compared to a reference process. These patterning enhancements are inherent properties of SIS. Also, the number of nanobreaks – a typical stochastic nano-failure – is reduced by at least one order of magnitude. Results were confirmed in an industrial use case, showing reduced defectivity in a logic chip with a 20 percent smaller tip-to-tip critical dimension at a similar LCDU as a standard EUVL process.
The work was performed in collaboration with ASM and ASML.
"This is a great example of how the integration of knowledge and combined efforts from multiple domains and ecosystem partners will enable a path to scale to N3 and beyond," said Greg McIntyre, director of advanced patterning at IMEC, in a statement.
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