ST preps second neural network IC

September 22, 2017 //By Peter Clarke
ST preps second neural network IC
STMicroelectronics is designing a second iteration of the neural networking technology that the company reported on at the International Solid-State Circuits Conference (ISSCC) in February 2017.

This is set to be a product as a distinct from what is described as a demonstrator IC, and it is a technology that CEO Carlo Bozotti is enthusiastic about. Bozotti spoke about the technology during a keynote his keynote speech for the combined European MEMS, Imaging and Sensors summits, held in Grenoble, France. The European summits are hosted by the MEMS and Sensors Industry Group under the auspices of industry organization SEMI.

Bozotti said the technology could be used to distribute artificial intelligence throughout a system based on ST32 microcontrollers and sensors.

Speaking in the main program of the event Thomas Boesch, a member of the technical staff at ST, said his company is now working on a new implementation of the technology for accelerating convolutional neural networks; one that is more optimized and more targeted.

In his talk Boesch laid out the architecture and performance of the dedicated deep convolution neural network (DCNN) SoC re-iterating much of what was disclosed at ISSCC (see ST, FDSOI lead machine learning spike at ISSCC).

The SoC is implemented in 28nm FDSOI and has an extended dynamic voltage and frequency scaling (DVFS) regime that allows it to operate with a clock frequency of 200MHz at 0.575V and then up to 1.1GHz clock frequency at 1.1V.

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