Tools and techniques for variation-aware design of custom IC designs

December 19, 2017 //By Art Schaldenbrand
Tools and techniques for variation-aware design of custom IC designs
This article focuses on an important topic for custom IC designers: variation-aware design (VAD). The emergence of high-speed simulators such as Spectre APS has reduced simulation time, thus allowing designers to spend more effort to explore allocating design margins based on process variation.

Not only can designers use the Cadence Virtuoso ADE Product Suite to analyze simulation results to verify a design is specification compliant, they can also use it to reduce the effect of process variation on a design. Solving this problem requires more than fast simulation, it requires adopting new tools and methodologies.

Minimizing the effect of process variation is an important consideration because it directly impacts the cost of a design. From Pelgrom’s Law, it is understood that the device mismatch due to process variation decreases as the square root of increasing device area, see Note 1. For example, to reduce the standard deviation, sigma, of the input offset voltage of a differential pair from 6mV to 3mV, means that the transistors size needs to be increased by four times.

By increasing transistor size, the die cost is also increased since die cost is proportional to die (and transistor) area. In addition to increasing cost, increasing device area may degrade performance due to the increased device parasitic capacitances of the larger devices. To maintain performance, power dissipation may need to be increased using more current to drive the larger parasitic capacitances of the larger devices. The result is that analog circuits don’t scale down as quickly as digital circuits, that is, to maintain the same level of analog performance has historically required something like roughly the same die area from process generation to process generation.

If an ADC requires 20% of the die area of a product at 180nm, then after two process generations at the 90nm process node, the die area of the ADC and digital area have become roughly equivalent. After two more process generations at the 45nm process node, the ADC requires 4x the area of the digital blocks, see Note 2. The example that has been presented is exaggerated since the logic in an ADC also scales, however, the basic concept that process variation is an important design consideration for analog design is valid.

Traditionally, the main focus of block-level design has been on parasitic closure, that is, verifying the circuit meets specification after layout is complete and parasitics from the layout have been accounted for in simulation. This focus on parasitic closure meant that there was only limited supported for analyzing the effect of process variation on design. During the design phase, sensitivity analysis allowed a designer to quantitatively analyze the effect of process parameters on performance. During verification, designers have used corner analysis or Monte Carlo analysis to verify performance across the expected device variation, environmental, and operating conditions.

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