It is not clear from TSMC's press release whether N4P is a 5nm process or a 4nm process – but as these node names are arbitrary and do not refer to any particular critical dimension it probably does not matter.
The company describes N4P as "the third major enhancement of TSMC's 5nm family."
From an SoC developers point of view what matters most is how it performs as benchmarked against a known process such as N5.
N4P will deliver an 11 percent performance boost over N5 and a 6 percent boost over N4, TSMC said.
Compared to N5, N4P will also deliver a 22 percent improvement in power efficiency and a 6 percent improvement in transistor density.
In addition, N4P lowers process complexity and improves wafer cycle time by reducing the number of masks required. This is presumably through greater use of extreme ultraviolet lithography for critical layers.
With the emphasis on performance N4P is being aimed at high performance computing chip and smartphone application processors.
The first products based on N4P technology are expected to tape out in 2H22.
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