TSMC launches N12e process for low Vdd

August 25, 2020 //By Peter Clarke
TSMC launches N12e process for low Vdd
Foundry TSMC used its virtual European technology symposium to launch its N12e process, the latest in a series of ultra-low leakage (ULL) manufacturing processes.

This series of processes has been developed by TSMC to minimizes power consumption for battery-operated and other edge devices and to allow near-threshold logic design. N12e is based on the TSMC 12FFC+ technology which in turn came from 16nm FinFET technology introduced in 2013. The N12e was made available to some customers a while ago, and first risk production started in 1Q20.

The process is aimed at AI, 5G-enhanced IoT and mobile markets amongst others.

Kevin Zhang, senior vice president of business development at TSMC, compared the node with the previous ULL node at 22nm. Zhang said N12e provides 50 percent more performance at the same power consumption (x1.5) while reducing power consumption at the same performance by 55 percent (x0.45). The logic density is improved by 75 percent (x1.75). Vdd can be taken down to 0.4V.

Related links and articles:

www.tsmc.com

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