TSMC preps for 'chiplet' style manufacturing in 2021: Page 2 of 2

May 09, 2019 //By Peter Clarke
TSMC preps for 'chiplet' style manufacturing in 2021
Leading foundry chipmaker TSMC has revealed that it expects to start 'chiplet' style production with its System-on-Integrated Circuit (SoIC) 3D packaging system in 2021.

The chiplet approach is likely to hinge on standardization of interfaces so that known-good-die (KGD) or chiplets can be placed in a library and then selected for assembly using die-to-die bonding. The result should make for quicker and lower cost design and assembly of complex chips.

Last month Cadence announced that TSMC had qualified its EDA tools as being suitable for the design SoICs . A full suite of Cadence digital and signoff, custom/analog, and IC package and PCB analysis tools have been optimized for TSMC’s SoIC chip stacking technology.

At the same time Ansys and Synopsys announced that their tools and design platform have been certified for SoIC chip-stacking technology.

Related links and articles:

www.tsmc.com

www.cadence.com

www.synopsys.com

News articles:

Broadcom preps for 7nm tape-outs in 2017

EDA tools support TSMC InFO 3D packaging


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