TSMC to present 5nm CMOS, 22nm STT-MRAM at IEDM

October 15, 2019 //By Peter Clarke
TSMC to present 5nm CMOS, 22nm STT-MRAM at IEDM
Leading foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has at least two significant papers at the International Electron Devices Meeting (IEDM) coming in December 2019.

The first is a paper describing the company's 5nm CMOS technology platform, which is made using extreme ultraviolet (EUV) lithography, and is likely to further establish TSMC as the world's most advanced chip manufacturer. The 5nm CMOS process is optimized for both mobile and high-performance computing and offers nearly twice the logic density (1.84x) and a 15 percent speed gain or 30 percent power reduction over the company's 7nm process.

TSMC has engaged with its customers on 5nm and multiple tape outs had been achieved prior to April 2019 (see TSMC declares 5nm process ready for design). The researchers say high-volume production is targeted for 1H20.

With learning from the successful introduction of the 7nm process TSMC has been able to apply EUV lithography to more layers and reduced the total mask count compared with the 7nm process. The transistors include channels engineered for high mobility. The SRAM can be optimized for low power of high performance and the researchers state that the high-density version 0.021 square microns is the highest density SRAM ever reported.

Next: Second paper

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.