The research company uses the term Dynamic Flash Memory (DFM) although the memory is volatile. The advantages over conventional 1T-1C DRAM include higher density, speed, longer refresh period and the research company is looking for partnerships to demonstrate the ease adoption of DFM as a DRAM replacement.
Unisantis also makes the point that unlike so-called emerging non-volatile memory technologies such as MRAM, ReRAM, FRAM and PCM, DFM does not involve adding additional materials beyond a standard CMOS process. However, it should be noted that there are some ferroelectric and ReRAM technologies that are also in that category.
DFM was presented this week in a paper entitled 'Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)' at the 13th IEEE International Memory Workshop (IMW), by its inventors, Koji Sakui and Nozomu Harada from Unisantis. However, it appears that this is a largely theoretical paper and not tied to a particular silicon implementation or process node. The company states the technology is suitable for both stand-alone and embedded memory applications.
Cross-point access to an array of vertical transistors gives 4F2 memory cell area. Source: Unisantis Electronics.
Unisantis said that because DFM does not rely on capacitors to save its state it has fewer leak paths. Charge is stored along the length of the vertical transistor, which would have a 50:1 aspect ratio in a 20nm DRAM manufacturing process. The vertical transistor offers higher density compared with convential DRAMs and the possibility of cross-point access. It also allows block erase similar to a flash memory. The company claims this all adds up to significant speed and power consumption improvements compared to DRAM.
Sakui told eeNews Europe that there is the capability to extend the refresh by many factors up to 100x – taking refresh up to seconds, at least, using DFM.
DRAM development has effectively stopped at about 15nm feature size and 16Gbit memory capacity per IC and there is now discussion of DRAM following the same path as NAND flash memory and going to multiple layers as 3D-DRAM.
The cross-point structure made of SGTs used within DFM theoretically allows continued 2D scaling of a much-improved 4F2 memory cell, although Unisantis did comment on how to effect a selector device in such a memory cell. Selector devices, such as a pass transistor selector diode are required to prevent sneak-paths circumventing the cross-point selection.
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