The company's timetable has slipped from some earlier reports in 2018 and 2019 but now Tachyum (Santa Clara, Calif.) reports the master chip layout has been completed and about 90 percent of the physical design verified.
The design targets TSMC's EUV-enabled 7nm FinFET manufacturing process and Tachyum's CEO Radoslav Danilak said that he wants to have an FPGA-board emulation of the design in 3Q20 followed by tape-out before the end of the year. Samples with customers in 1Q21 followed by production starting in 2Q21 and volume production in 2H21.
Given that silicon wafers on a leading-edge process can spend three months or more just moving through a wafer fab the timing still seems breathtakingly fast. "It's tight, but not impossible. That's why we will be going for a split tape-out," said Danilak.
The fab will be able to start on bottom layers and then receive information about the upper metal connections at a later date; a method used to overlap design engineering and manufacturing cycles. It is probably not something that TSMC would do with every customer but Danilak has built up a track record in previous employment with the likes of Nvidia, SandForce and Skyera.
The Prodigy processor is aimed at the Data Center but it intends to beat out the competition by being a Universal Processor that can do general-purpose work and high-performance computing work in the style of x86 and ARM and also artificial intelligence (AI), deep machine learning (ML), explainable AI, biological AI and other AI disciplines within a single chip.
There are considerable energy consumption, resource utilization and cost benefits that accrue from being able to simplify the architecture and network of the data center, Danilak argued and in addition Prodigy will offer great scalability and PPA benefits at the device level.
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