Using deep wells in analog IC design

May 18, 2015 // By Peter Clarke
Using deep wells in analog IC design
Keith Sabine, product manager at EDA firm Pulsic, discusses how to add a deep n-well in an analog or mixed-signal IC as a means of providing additional isolation from noise sources.

On a conventional CMOS process (see figure 1), NMOS devices are formed in a P well or substrate connected to ground (or the most negative supply in the circuit). PMOS devices are formed in an N well connected to the most positive supply.

Figure 1: A typical CMOS inverter shown in cross section. Substrate noise currents are shown as red lines.

Substrate noise caused by minority carrier injection into the substrate and well can be collected by the use of well taps and/or guard rings. An additional problem exists in that capacitive coupling of noise from the well to the substrate means that more noise reaches the supply. In digital circuitry this is usually not a problem owing to the relatively high noise immunity of logic gates. However in analog design, for example a 12-bit ADC, noise can be a serious problem. A variety of techniques can be used to minimize this noise, for example by keeping analog devices surrounded by guard rings, or using a separate supply for the substrate/well taps. However guard rings alone cannot prevent noise coupling deep in the substrate, only surface currents.

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