Xilinx introduces HDMI 2.1 IP subsystem

February 05, 2019 //By Ally Winning
Xilinx introduces HDMI 2.1 IP subsystem
Xilinx has introduced a complete HDMI 2.1 IP subsystem core, enabling Xilinx devices to transmit, receive and process up to 8K (7680 x 4320 pixels) UHD video.

Xilinx’s high-speed I/O transceivers are capable of handling HDMI 2.1 data rates and the native 8K interfaces supported by HDMI 2.1. The new IP will make it possible to replace several devices that support processing, compression, high-quality analytics and decision-making with a single Xilinx device.

“Today’s professional AV and broadcast markets continue to demand higher resolution, higher frame rates and high dynamic range,” said Ramesh Iyer, director of marketing, Pro AV and Broadcast market, Xilinx. “Our customers can now implement the complete HDMI 2.1 interface on-chip, creating highly-integrated designs that can natively handle 8K processing. And customers can combine this functionality with 8K lightweight mezzanine codecs for 8K over IP streaming, reducing real-estate, power consumption and BOM costs.”

Xilinx will demonstrate the HDMI 2.1 IP subsystem at booth 15-D240, ISE Integrated Systems Europe, RAI Amsterdam, February 5-8.

More information

www.xilinx.com

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